
SV51012
2014.01.10
Supported JTAG Instruction
IDCODE (32 Bits)
10-3
Family
Member Code
Version (4 Bits)
Part Number
(16 Bits)
Manufacture
Identity
LSB (1 Bit)
(11 Bits)
D3
0000
0010 1001 0001 000 0110 1110
1
0001
D4 (20)
0000
0010 1001 0000 000 0110 1110
1
0001
D4 (21)
0000
0010 1001 0001 000 0110 1110
1
Stratix V GS
D5
0000
0111
0010 1001 0000 000 0110 1110
1
0111
D6
0000
0010 1001 0001 000 0110 1110
1
0100
D8
0000
0010 1001 0000 000 0110 1110
1
0100
E9
0000
0010 1001 1001 000 0110 1110
1
Stratix V E
EB
0000
0101
0010 1001 1000 000 0110 1110
1
0101
Supported JTAG Instruction
Table 10-2: JTAG Instructions Supported by Stratix V Devices
JTAG Instruction
SAMPLE / PRELOAD
Instruction Code
00 0000 0101
Description
? Allows you to capture and examine
a snapshot of signals at the device
pins during normal device
operation and permits an initial
data pattern to be an output at the
device pins.
? Use this instruction to preload the
test data into the update registers
before loading the EXTEST instruc-
tion.
? Used by the SignalTap ? II
Embedded Logic Analyzer.
(20)
(21)
The IDCODE is applicable for EH29 and HF35 packages only.
The IDCODE is applicable for KF40 package only.
JTAG Boundary-Scan Testing in Stratix V Devices
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